TSMC 2nm and the AI Chip Race in 2026: N2 Ramp, Intel 18A, Samsung SF2

Last Updated: September 2026

The TSMC 2nm AI chip story changed character over the summer. In July, TSMC reported that its N2 node was already 3% of wafer revenue, and in September Apple put the first 2nm smartphone processor, the A20 Pro, into the iPhone 18 Pro. Yet the biggest AI accelerators shipping this quarter, including Nvidia’s Rubin, still sit on a 3nm-class process. The constraint on AI silicon is no longer just the transistor node. It is the whole chain: wafers, HBM4 memory, and CoWoS packaging.

That distinction matters because most coverage still treats the race as a scoreboard of nanometer labels. This analysis walks through what is actually verified as of late September 2026: how far the N2 ramp has come, where Intel 18A and Samsung SF2 really stand, what the packaging and memory numbers imply, and which claims from our July version we now retract or downgrade. You leave with a decision framework rather than a headline.

What this covers: what changed since July 2026, the physics of gate-all-around, the N2 ramp and its economics, a worked yield-and-cost model, the Intel and Samsung challenges, the packaging and HBM4 bottleneck, geopolitics, failure modes, and a practical watch list.

What Changed for September 2026

Our July edition was written before TSMC’s second-quarter call, before Apple’s iPhone 18 Pro launch, and before Intel’s second-quarter results. Several statements in it were either stale or too confident, so here is the plain list of changes.

N2 is now visible in the financials. TSMC’s July 16 call put N2 at roughly 3% of second-quarter wafer revenue, against 30% for N3 and 33% for N5, on total revenue of about $40.2 billion and a gross margin of 67.7%. Management guided N2 to dilute gross margin by roughly 3 to 4 percentage points in the second half as the ramp absorbs start-up cost. In July we described N2 yields in a 65 to 75% band. That figure was an industry estimate, never a TSMC disclosure, and it remains one.

Capex and US investment rose. TSMC lifted 2026 capital spending guidance to $60 to $64 billion from $52 to $56 billion. On the same day it announced a further $100 billion of US investment, which the US Department of Commerce describes as bringing the company’s total US commitment to $265 billion across 12 leading-edge and packaging facilities.

The first 2nm consumer silicon is real. Apple unveiled the A20 Pro on September 9, 2026 as the first 2nm smartphone chip. AMD said its 256-core EPYC “Venice” is the first x86 server CPU on TSMC’s 2nm process, with rollout in the fourth quarter.

Intel’s status is more nuanced than we wrote. 18A is in volume manufacturing for a subset of Core Ultra Series 3 processors and the Xeon 6+ server part, and 18A-P has entered risk production. But external 14A demand is still unproven: a Piper Sandler note dated September 25 says several large companies are evaluating 14A, with no announced commitments.

Samsung’s yield claims need a discount. The 70% SF2P figure we repeated in July was a single report. Public estimates since then range from about 50% early in the year to “approximately 80%” in a September report, and none is a Samsung disclosure. Meanwhile Tesla’s AI5 has reportedly taped out at Samsung for its Taylor, Texas fab.

HBM4 moved from promise to production. Nvidia’s CEO said in June that all three HBM4 vendors were qualified and in production for Vera Rubin. We have also removed the July claim of per-pin speeds above 11 Gbps, because Rubin’s published configuration cites 6.4 GT/s HBM4, so the higher figure describes vendor headroom, not what ships.

Context and Background

For two decades the leading edge of logic was defined by one transistor architecture. The FinFET, introduced commercially at 22nm around 2011, lifted the channel into a vertical fin and draped the gate over three sides. Every node from 16nm to 3nm refined that idea. By 3nm, electrostatic headroom was running out: as gate lengths shrink, a gate that touches only three sides of the channel loses its grip, leakage rises, and the old bargain of smaller, faster and cooler at once weakens.

The 2nm class answers with gate-all-around (GAA) nanosheets, where the gate wraps the channel on all four sides. TSMC’s N2, Intel’s 18A and Samsung’s SF2 all adopt it, although each vendor names the transistor differently: Intel calls its version RibbonFET, Samsung uses multi-bridge-channel FET language, and TSMC simply says nanosheet. Understanding 2nm therefore means understanding a new device, not just a smaller one.

Why does this matter for AI specifically? Training and inference at scale are limited by power delivery, cooling and memory bandwidth far more than by peak clock speed. A hyperscaler that buys tens of thousands of accelerators cares about performance per watt at rack scale, because each percentage point of efficiency compounds across the electricity bill and the cooling plant. GAA delivers most of its benefit in the power dimension, which is why the node transition and the AI capex cycle are the same event seen from two angles. Our hyperscaler custom AI silicon analysis shows how that pressure pushes cloud providers to design their own accelerators, all of which still depend on the same few foundries.

The competitive structure is the second piece of context. TSMC has dominated leading-edge foundry manufacturing for years, and one September report cited in this research put its share of advanced AI foundry output at about 95%. Intel and Samsung are the only other companies with volume GAA processes, and Rapidus in Japan is the newest entrant, targeting 2027. For the Intel side of the story in detail, see our Intel 18A-P foundry versus TSMC analysis.

The third piece is that a node name is a marketing label. “2nm” does not correspond to any physical dimension on the die. Foundries compare themselves on density, performance at a given power, and cost, and those comparisons are always against a vendor-chosen baseline. TSMC’s own public framing is available in its investor relations materials, and those are the useful primary source for the claims it does make.

The TSMC 2nm AI Chip Stack: Where N2 Really Sits in AI Silicon

A TSMC 2nm AI chip is not yet the typical AI accelerator. As of September 2026, N2 leads in mobile and server CPUs, while flagship GPUs such as Nvidia’s Rubin use a 3nm-class process with CoWoS-L packaging and HBM4. N2 reaches AI accelerators next, gated by wafer allocation, HBM4 supply and packaging capacity rather than by transistor readiness alone.

Figure 1: An AI accelerator is three supply chains that must converge: logic wafers, HBM4 stacks and advanced packaging.

Figure 1 shows why the node label misleads. The package contains a logic die from a leading-edge foundry, several HBM stacks from a memory maker, and a silicon interposer or bridge from a packaging line. Those three flows converge on one assembly step, and the slowest one sets the shipping rate for the entire rack.

The N2 ramp in numbers

TSMC entered N2 high-volume manufacturing in the fourth quarter of 2025. By the second quarter of 2026 it accounted for about 3% of wafer revenue. That is a small share, but the shape matters: N3 took several quarters to reach 30%, and N2 is climbing from a similar starting slope with a much larger installed base of customers waiting.

On capacity, secondary reporting that summarises TSMC’s own roadmap presentations says N2 wafer-out capacity should be about 45% higher than N3B in its first year, reaching roughly 90,000 wafer starts per month by the end of 2026. Other outlets have circulated figures of 100,000 to 140,000 wafers per month. Treat those as unofficial trade-press estimates with wide error bars, since TSMC does not publish monthly wafer-start numbers. The fabs involved are the Hsinchu Baoshan site (Fab 20) and the Kaohsiung site (Fab 22), with Kaohsiung’s later phases reported as equipped and ramping in the second half.

TSMC has also told investors it expects N2 and A16 capacity to grow at about a 70% compound rate through 2028. If that holds, N2 stops being scarce sometime in 2027 or 2028, but not before the largest customers have locked in their allocations. One trade-press source claims lead times of 78 to 156 weeks and bookings well into 2028; we could not corroborate that from a primary source, so consider it directional only.

What GAA actually changes

In a FinFET, the channel is a vertical fin and the gate covers three sides. The underside stays ungated, and that is where leakage sneaks through as dimensions shrink. A GAA device stacks several horizontal silicon sheets and grows the gate material completely around each one. Electrostatic control improves, so the transistor turns off harder and leaks less at short gate lengths.

There is a second, less-discussed benefit. FinFET width is quantised, because you add drive current by adding whole fins. Nanosheet width is a continuous design knob. A designer can widen sheets in a high-performance datapath cell and narrow them in a low-power cell on the same wafer. TSMC also offers what it calls NanoFlex design flexibility, which mixes cell heights on one die. For an AI die that contains dense, low-voltage matrix engines next to fast control logic, that flexibility is directly useful.

Vendor PPA claims should be read carefully. TSMC’s public N2 comparison against N3E cites a speed gain of roughly 10 to 15% at the same power, or a power reduction of roughly 25 to 30% at the same speed, plus a logic density increase of around 15%. These are vendor-stated, node-to-node figures for a specific test structure, not measurements of a shipping AI product. In TSMC’s July call, the A14 comparison against N2 was framed similarly: 10 to 15% speed at the same power or 25 to 30% lower power at the same speed. Each generation therefore buys a normal single-digit-to-low-double-digit step, not a doubling.

Backside power: which node, exactly

Backside power delivery moves the power network to the wafer’s rear so the front metal stack can carry signals. Intel ships its version, PowerVia, on 18A now. TSMC’s version, Super Power Rail, belongs to A16, which TSMC has positioned for volume production in the second half of 2026, and one industry report says Nvidia is the lead A16 customer for its Feynman generation. We could not find a September confirmation of A16 volume shipments, so we describe A16 as scheduled, not shipping.

The important point is sequencing. TSMC deliberately separated the GAA transition (N2) from the backside power transition (A16) so that only one hard change happens per node. Intel bundled both into 18A, which is higher variance but produced a genuine first on backside power. Samsung’s backside variant, SF2Z, is targeted later. Being first on a feature is not the same as winning the customer, because customers buy yield, schedule and ecosystem.

Who is on N2

Apple is the anchor mobile customer, and the A20 Pro is the public proof. AMD’s Venice server CPU is the first confirmed data-centre part on N2, and AMD has said its MI400-generation accelerators are part of the same platform push. AMD’s Helios rack pairs 72 MI455X GPUs with 18 Venice CPUs and, per AMD’s claims, carries about 31 TB of HBM4 across the rack, with shipments starting at the end of the third quarter and ramping into the first half of 2027. Which node AMD’s accelerator compute dies use has been reported as N2 by trade press, but we treat that as reported rather than confirmed.

Other names appear in supplier-chain reporting: MediaTek and Qualcomm for phone chips, Fujitsu for a CPU, and Nvidia for A16-generation GPUs. Reporting that a company has “taped out” or “booked” N2 is not the same as volume revenue, so we list only Apple and AMD as clearly public.

Deeper Analysis: The Economics of N2 and the Worked Yield Model

Investors and engineers both ask the same question: is 2nm cheaper or just better? The honest answer is that it is better per watt and more expensive per wafer, and the AI die-size regime makes yield the swing factor.

Wafer price and margin

Trade press, citing supply-chain sources, puts an N2 wafer at roughly $30,000, about 20 to 50% above N3. TSMC has not confirmed a price. Separate reporting from late 2025 said TSMC planned price increases of about 3 to 10% on advanced nodes for 2026 and further increases through 2029. What TSMC does disclose is its own margin path: the July call guided third-quarter gross margin to 65 to 67% and flagged that N2 ramp costs would drag second-half margin by 3 to 4 points, with overseas fab expansion adding a further 2 to 3 points initially. That is management telling you the new node is costly to bring up, even for the company with the strongest yield learning in the industry.

A worked yield model

The illustration below uses a simple Poisson yield model, yield equals e raised to the power of minus die area times defect density. The numbers are illustrative, chosen to show sensitivity, and are not any foundry’s real defect density.

Take a near-reticle accelerator die of 800 mm² (8 cm²). On a 300 mm wafer, a common gross-die approximation gives about 64 candidate dies after edge loss. At the assumed $30,000 wafer price:

Assumed defect density	Poisson yield	Good dies per wafer	Cost per good die (illustrative)
0.10 per cm²	about 45%	about 29	about $1,040
0.05 per cm²	about 67%	about 43	about $700
0.02 per cm²	about 85%	about 55	about $550

Now split the same function into four chiplets of 200 mm² each. At 0.10 defects per cm², each small die yields about 82%, so a known-good-die strategy recovers most of the loss, although the design pays for extra packaging and die-to-die interconnect. That is the quiet reason advanced packaging and chiplets grow together: at a new node with immature defect density, small dies protect cost.

Figure 2: Illustrative Poisson yield and cost per good die. Numbers are for sensitivity only.

Note what the table implies about the July “65 to 75% yield” claim. Industry yield estimates are usually quoted for small mobile dies, where 100 mm² dies yield far higher than an 800 mm² die at the same defect density. A 70% yield on a phone SoC tells you little about a reticle-size AI die. That is a principal reason the first N2 products were phone and CPU chiplets, and why large-die AI parts tend to arrive a year or more later on a mature process variant.

Roadmap: N2, N2P, A16, A14

Figure 3: The GAA node family tree. TSMC sequences GAA, then backside power, then a further node; Intel bundled both early.

Figure 3 lays out the family tree. TSMC’s cadence is N2, then an enhanced N2P, then A16 with backside power, then A14. On the July call TSMC said A14 development is on track, that internal test vehicles show close to 90% device performance and close to 90% yield on a 256 Mb SRAM, that pre-production is 2027 and that volume production is 2028. Company-stated SRAM yield is a very early indicator, since SRAM arrays are regular and forgiving compared with a full logic die, so read it as a milestone rather than a promise of product yield.

For AI buyers the practical reading is that N2P and A16 are the likely homes of the first large accelerator dies, because they combine a process that has had a year of learning with the power-delivery gains that matter most for kilowatt-class parts. Our TSMC A14 and Intel 14A foundry race analysis covers the next round in more depth.

The Challengers: Intel 18A, Samsung SF2 and Rapidus

For the first time in a decade there are three companies with volume GAA processes, and a fourth trying to join. But volume capability and customer adoption are different things, and the evidence differs sharply between the challengers.

Intel: technically credible, commercially unproven

Intel’s second-quarter 2026 results, reported July 23, showed revenue of $16.1 billion, up 25% year over year, with Intel Foundry revenue of $5.8 billion, up 31%. Most of that foundry revenue is Intel’s own products flowing through its manufacturing arm, so it is not evidence of external demand. Secondary reporting put the foundry operating loss at about $2.1 billion for the quarter, which we cite as reported rather than verified against the filing.

On technology, Intel says 18A is in high-volume manufacturing for a subset of Core Ultra Series 3 (Panther Lake) processors, that the Xeon 6+ server processor uses 18A, and that 18A-P, the performance-enhanced variant aimed at outside customers, has entered risk production on the timeline given to customers. That is a real milestone: GAA plus backside power in volume is something neither TSMC nor Samsung can claim today.

The external picture is thinner. The one named outside collaboration in the second-quarter release is Fortinet, for a security processor. A Piper Sandler note dated September 25 says Amazon, Apple, AMD, Google, Tesla, Microsoft, Nvidia and Qualcomm are all reportedly evaluating 14A, but no commitments are public, and the note argues Intel needs an anchor customer by late 2026 or early 2027 to justify the capital. Evaluation is not adoption: a customer running test chips through a process design kit is a small step compared with committing a flagship product. We covered the foundry angle in our Intel 18A-P analysis, and the conclusion still holds: Intel’s problem is customer trust and ecosystem depth, not the transistor.

Samsung: a real second source, with noisy yield numbers

Samsung’s SF2 struggled in 2025, and public yield figures since then have been inconsistent. Trade reports in January cited about 50% for the Exynos 2600, later reports cited about 60%, and a September report said “approximately 80%.” None comes from Samsung. The spread itself is informative: yield depends on die size, the product and the measurement point, and outside observers rarely know which one is being quoted. Our earlier 70% SF2P figure belongs in the same bucket.

The stronger evidence is customers. Samsung engineers reported that Tesla’s AI5 chip has taped out at Samsung and is cleared for 2nm production at the Taylor, Texas fab, with volume production expected in the second half of 2027. Tesla reportedly taped out slightly different AI5 versions at both Samsung and TSMC, which is exactly what dual sourcing looks like in practice. In September, OpenAI’s Korea team confirmed joint work with Samsung on chips, though which logic node or product is involved remains unconfirmed, and a reported large Broadcom-Samsung foundry memorandum has not been independently verified. The defensible reading is that Samsung is becoming a credible second source for customers who cannot get enough TSMC capacity, not that it is displacing TSMC.

Rapidus and the rest

Rapidus, the Japanese government-backed foundry, demonstrated 2nm GAA prototype transistors in 2025 and targets mass production in 2027 at its Hokkaido fab. It has raised private and public funding, including a reported $1.7 billion round in early 2026, and says it is talking to dozens of potential customers. It is a strategic bet on short-turnaround single-wafer processing and on diversification, and it should be treated as an unproven entrant until it announces production customers and yields. It does not change 2026 or 2027 accelerator supply.

Packaging and HBM4: The Real Bottleneck

The wafer is only the beginning. A modern accelerator is a system in a package, and in 2026 the binding constraints sit outside the logic die.

CoWoS and SoIC capacity

TSMC’s CoWoS (Chip on Wafer on Substrate) technology places logic dies and HBM stacks on a silicon interposer. Trade reports say TSMC’s CoWoS capacity is heading to roughly 120,000 to 140,000 wafers per month in 2026, with outsourced assembly partners adding another 50,000 to 60,000 wafers of capacity for an industry total that could approach 200,000. TrendForce reported in June that the supply-demand gap was around 20% and might narrow to about 10% by the end of 2026. TSMC has said its CoWoS capacity has grown at more than 80% a year from 2022 to 2027, and SoIC (the 3D stacking technology) at about 90%.

A successor called CoPoS, which uses panel-level rather than wafer-level substrates, is reported to reach pilot production around mid-2027 with broader use in 2028 or 2029. Until then CoWoS-L, the variant with local silicon bridges that Rubin uses, is the workhorse. One trade source estimates Nvidia holds around 60% of CoWoS capacity, which we cite as an estimate; even so, it explains why other accelerator vendors race for the remainder.

HBM4 in production

Nvidia’s Jensen Huang said in early June that Samsung, SK hynix and Micron were all qualified and in production for Vera Rubin, with customer shipments in the third quarter. Analyst estimates of the split are unofficial: SK hynix in the range of 60 to 70%, Samsung around 25 to 30%, Micron the rest. HBM4 doubles the interface to 2,048 bits and moves to 32 channels per stack. Rubin’s published configuration is eight stacks totaling 288 GB and roughly 13 TB/s of bandwidth, and AMD’s Helios rack claims about 31 TB of HBM4 across 72 GPUs, or roughly 430 GB per GPU. Samsung also said it shipped first HBM4E samples on September 9, according to trade reporting.

For supply-chain analysis this means memory allocation is now a first-order gate. Our Micron and HBM supercycle analysis goes deeper on the memory side, including why HBM consumes disproportionate DRAM wafer capacity.

Figure 4: The delivery sequence for an AI rack. Each hand-off can become the gating step.

Geopolitics, Location and Policy

Where chips are made now matters as much as how. Taiwan still hosts the overwhelming majority of leading-edge logic, and Korea hosts most HBM. Every diversification effort is a partial hedge that takes years to matter.

TSMC’s July announcement of an additional $100 billion in the United States, per the US Department of Commerce, brings its stated US commitment to $265 billion across 12 leading-edge and advanced packaging facilities. TSMC has said Arizona’s second fab phase is on track to begin N3 production in the third quarter of 2027, with a third phase targeting N2 later in the decade, per trade-press summaries of TSMC’s roadmap. So Arizona will not host N2 AI accelerators in volume before roughly 2028 to 2029, and advanced packaging in the US lags even that. The January 2026 US-Taiwan trade agreement, which the Commerce Department framed around $250 billion of Taiwanese chip investment, is the policy backdrop; we did not verify its tariff terms in detail, so read the official fact sheet before relying on specifics.

Our July edition covered South Korea’s reported $576 billion AI and chip plan announced June 29, centred on Samsung and SK hynix. We did not re-verify that figure this month, and readers should treat it as a headline commitment whose milestones matter more than its total. The strategic logic is unchanged: if memory and packaging are the constraints, state money flows to memory and packaging.

Two structural facts follow. First, geographic concentration is a risk that customers now price and hedge, which is one reason Samsung’s Texas fab and Intel’s US fabs get customer attention beyond their technical merit. Second, overseas fabs cost more to run: TSMC itself expects overseas expansion to dilute gross margin by about 2 to 3 points at first, widening to 3 to 4 at scale. Someone pays that, either the customer or the foundry.

Decision Matrix: Which Foundry for Which Job

The matrix below is analytical, not a recommendation to buy any security. It summarises fit by workload for a chip designer choosing a 2027 to 2028 process.

Use case	TSMC N2 / N2P	TSMC A16	Intel 18A / 18A-P	Samsung SF2 / SF2P
Flagship mobile SoC	Proven, Apple shipping	Overkill on cost	Limited ecosystem	Viable, yield-sensitive
Reticle-size AI accelerator	Possible via chiplets	Best fit, backside power	Possible, less proven	Second source only
Server CPU chiplet	AMD Venice shipping	Later	Xeon 6+ in-house	Early
Custom hyperscaler ASIC	Default, with packaging	Candidate	Emerging, needs anchor	Dual-source option
US-based supply requirement	Arizona N3 in 2027	Not yet	Available in US	Taylor in 2027
Packaging pairing	CoWoS mature	CoWoS mature	EMIB and Foveros	Partners vary

The pattern is consistent: TSMC wins where risk aversion and ecosystem dominate, Intel wins where US-based volume and backside power matter, and Samsung wins where a second source or price flexibility matters. None of the three wins everywhere.

Trade-offs, Gotchas, and What Goes Wrong

The optimistic reading of 2026 is a clean, well-supplied race in which cheaper, more efficient transistors flow to every accelerator vendor. Several things can break that story, and most of them are ordinary engineering and economics rather than dramatic events.

Yield learning can stall. GAA nanosheets are a new device with new failure mechanisms: sheet-release etch, inner spacer formation and work-function metal fill all have to be uniform around a wrapped channel. A yield plateau at any of the three foundries tightens the whole market, because there is very little slack. The reported yield numbers, whether 65 to 75% for TSMC or 50 to 80% for Samsung, are unofficial snapshots for unknown die sizes. Do not build a plan on them.

Cost per transistor has stopped falling. Extreme ultraviolet lithography, extra mask layers, and now backside-power steps mean each node costs more per wafer than the last. You gain performance per watt but not cheaper logic, and with reticle-size AI dies the wafer price and yield multiply directly into the bill of materials. The worked model above shows a per-die cost swing of nearly two times between weak and strong yield, which is larger than the entire nominal generational gain.

Thermals can eat the power gain. Backside power moves heat paths, and thinned wafers can concentrate hot spots. A device that saves 25% power at the transistor can still throttle if the package cannot remove the heat. This is why our rack-scale analyses spend so much space on cooling, and why the Nvidia GB300 NVL72 architecture piece is a good complement to this one.

Single points of failure are everywhere. One foundry, one interposer technology, three memory vendors, and a small number of extreme ultraviolet tool suppliers. A fault in any stage in Figure 4 halts the line. Dual sourcing helps only if the design has been qualified on both sources, and that qualification takes quarters.

Design complexity is a barrier. Tape-out costs at the leading edge run to hundreds of millions of dollars; one trade source cites roughly $725 million of development cost per platform, an estimate we cannot verify. Few companies can afford that, so the customer base concentrates, which raises the stakes of each design and reinforces allocation power for the incumbents.

Capex is a bet on demand. TSMC’s $60 to $64 billion budget, Intel’s $6.2 billion of gross first-half capex, and Korea’s state-backed plans all assume AI demand continues. If it cools, the industry is left with expensive, under-used capacity, and the industry has seen that pattern before in memory and in earlier boom cycles. This is a structural risk, not a forecast; we take no view on demand.

Anti-patterns worth avoiding. Comparing “2nm” labels across vendors as if they were the same dimension; treating a taped-out chip as a shipping product; quoting a yield without a die size; and assuming that first on backside power means first on customer wins. Each of these has misled published analysis in the last twelve months.

Practical Recommendations

If you plan silicon, buy infrastructure, or simply follow the market, focus on signals that separate real progress from announcements. Watch yield claims only when they come with die size and a measurement point. Prefer quantities disclosed in filings, such as N2’s share of wafer revenue and capex guidance, over unofficial capacity estimates. Treat customer names as confirmed only when the customer or the foundry says so in a product launch or filing.

For engineering teams designing accelerators for 2027 and 2028, the pragmatic path is chiplet-first. Split the reticle-size die so that early-node defect density costs you a small die rather than a large one, reserve packaging slots early because CoWoS and HBM4 allocations are negotiated well ahead of wafers, and qualify a second source only if your product volume justifies the qualification cost.

A checklist for staying oriented through the rest of 2026:

• N2’s share of TSMC wafer revenue in the third-quarter report, and the gross-margin drag against the 3 to 4 point guide.
• Confirmation of A16 volume production and the first backside-power customer silicon.
• Whether Intel names a 14A anchor customer, and whether 18A-P moves from risk to volume production.
• Samsung’s Taylor fab progress and any named 2nm customer beyond Tesla.
• CoWoS supply-demand gap against the reported 20% to 10% path, and CoPoS pilot timing.
• HBM4 allocation splits and HBM4E qualification timing.
• Rapidus customer announcements ahead of its 2027 mass-production target.

This article is technology and supply-chain analysis only. It is not investment advice and does not recommend buying or selling any security.

Frequently Asked Questions

Is TSMC 2nm in volume production in September 2026?

Yes. TSMC began N2 high-volume manufacturing in the fourth quarter of 2025, and on its July 16 call it said N2 contributed about 3% of second-quarter wafer revenue. Apple’s A20 Pro, announced September 9, is the first 2nm smartphone chip, and AMD says its EPYC Venice is the first x86 server CPU on the node. Capacity remains tight, and TSMC expects N2 to dilute gross margin by roughly 3 to 4 percentage points in the second half of 2026.

Do Nvidia’s Rubin GPUs use 2nm?

No. Rubin uses a 3nm-class TSMC process with CoWoS-L packaging and eight HBM4 stacks, for a published 288 GB of memory per GPU. Nvidia began full production in mid-2026 with customer shipments in the third quarter. Industry reports say Nvidia’s later Feynman generation is the lead customer for TSMC’s A16 node, which adds backside power. That report is unofficial, so treat 2nm and A16 accelerators from Nvidia as a 2027-plus expectation rather than a confirmed product.

How does Intel 18A compare to TSMC N2?

Intel 18A combines GAA transistors (RibbonFET) with backside power (PowerVia) and is in volume for a subset of Core Ultra Series 3 processors and Xeon 6+. TSMC N2 has GAA but adds backside power later with A16. TSMC leads on ecosystem maturity, customer base and proven ramp record. Intel’s open question is external demand: reports say major firms are evaluating 14A, but no commitments are public as of late September 2026.

What is Samsung’s 2nm yield?

Samsung has not published a verified figure. Trade reports have ranged from about 50% early in 2026 to about 60% mid-year and about 80% in a September report, each for unspecified dies. The more reliable signal is customer activity: Tesla’s AI5 has reportedly taped out at Samsung for the Taylor, Texas fab, with volume expected in the second half of 2027. Yield claims without die size and date should be treated as directional only.

Why is CoWoS packaging such a bottleneck for AI chips?

CoWoS joins large logic dies and HBM stacks on a silicon interposer, and it needs specialised capacity that expanded later than wafer capacity. Trade reports say TSMC’s CoWoS capacity is heading toward 120,000 to 140,000 wafers per month in 2026, with the supply-demand gap around 20% narrowing toward 10% by year-end. Because packaging, HBM4 and logic wafers must all arrive together, the slowest of the three sets accelerator output regardless of the node used.

Will Rapidus or Samsung end TSMC’s dominance?

Not in the next two years on the available evidence. Samsung is a credible second source with a named Tesla program and Texas capacity coming in 2027, while Rapidus targets mass production in 2027 but has no announced volume customers or public yield data. Intel may win specific programs if it lands a 14A anchor customer. TSMC’s lead rests on ecosystem, packaging and demonstrated ramp delivery, which competitors need years to replicate.

Further Reading

• Intel 18A-P foundry versus TSMC: analysis for the Intel foundry case in depth.
• TSMC A14 and Intel 14A: the next foundry race for the 2028 generation.
• Micron and the HBM AI memory supercycle for the memory side of the bottleneck.
• Hyperscaler custom AI silicon analysis for who designs the chips these fabs build.
• How silicon photonics chips work for the interconnect side of the bandwidth problem.
• TSMC Q2 2026 earnings materials (primary source) and Intel’s second-quarter 2026 results (primary source).
• US Department of Commerce announcement on TSMC’s additional US investment (primary source).

By Riju — about