How Silicon Photonics Chips Work: Moving Data with Light (2026)

Last Updated: October 2026

A modern AI rack pushes so much data between accelerators that the copper traces connecting them have become the most expensive part of the design to cool, power and debug. Past roughly 200 gigabits per second per lane, an electrical signal stops being a clean waveform and starts being a fight against loss, reflections and crosstalk. The industry’s answer is to stop sending electrons over those last centimeters and send photons instead. Understanding how silicon photonics chips work is now a practical skill for anyone who designs, buys or operates AI infrastructure, because the switch in your next cluster may contain a laser-lit optical engine welded to its package.

This guide rebuilds the topic from the physics up and then climbs to the system level. You will see why a waveguide etched in silicon can guide light, how a Mach-Zehnder modulator and a microring modulator write bits onto a beam, how wavelength-division multiplexing multiplies a single fiber’s capacity, why the laser is the field’s awkward outsider, and what vendors have actually announced for co-packaged optics. We also dwell on what goes wrong: thermal drift, coupling loss, laser reliability and serviceability.

What this covers: the copper wall and the energy-per-bit argument, the four building blocks of an optical link, modulator physics, wavelength multiplexing, SOI fabrication, laser integration, co-packaged optics in 2026 (NVIDIA, Broadcom, TSMC, Ayar Labs, Lightmatter), failure modes, and a practical checklist.

Context and Background

Optical fiber has carried long-haul traffic for decades, and pluggable optical transceivers have connected data center switches for most of the last twenty years. What changed is the distance at which optics beats copper. Inside a rack, passive copper cables once covered everything. As per-lane signaling rates climbed through 56, 112 and now 224 gigabits per second (Gb/s), the usable reach of passive copper shrank to roughly a meter or less, and equalization circuitry inside the transceiver chips grew hungrier. Industry commentary, including a SemiEngineering analysis of AI data center interconnects, argues that interconnects are becoming a first-order share of data center energy, a figure often quoted near 30 percent for the most network-heavy designs. Treat that percentage as an industry estimate that varies strongly by architecture rather than a universal constant.

Silicon photonics is the manufacturing idea that makes optics cheap enough to move closer to the chip. Instead of assembling discrete lenses, crystals and lasers by hand, you pattern waveguides, modulators and detectors on the same kind of silicon wafer, in the same kind of foundry, that produces logic chips. The dominant platform is silicon-on-insulator (SOI): a thin crystalline silicon layer on top of a buried silicon dioxide layer. Foundries such as GlobalFoundries (its Fotonix platform) and TSMC (its COUPE family) now offer photonic process design kits, which lets fabless companies draw optical circuits much as they draw transistors.

The result is a spectrum of products. Pluggable transceivers (400G, 800G, 1.6T) already use silicon photonics inside the module. Co-packaged optics (CPO) moves the optical engine onto the same substrate as the switch or accelerator. Optical I/O chiplets, the approach championed by Ayar Labs and Lightmatter, go a step further and aim to replace the electrical die-to-die and die-to-memory links themselves. If you want the system-level market view first, our companion piece on silicon photonics and co-packaged optics in the data center covers deployment economics; this article concentrates on the device physics and architecture underneath.

One caution on sourcing. Silicon photonics is a field where vendor press releases dominate the public record. Throughout this post, figures attributed to a company are that company’s claims, and numbers I derive myself are labeled illustrative. Where a number is a widely used engineering rule of thumb rather than a measurement from a specific product, I say so.

The Core Architecture: An Optical Link in Four Parts

A silicon photonics link converts electrical data to modulated light and back using four components: a laser that supplies a continuous carrier, waveguides that route it, a modulator that encodes bits onto it, and a photodetector that turns pulses back into current. Everything except the laser is typically fabricated on a standard SOI wafer in a CMOS-compatible process.

Figure 1: The four-part optical link at the heart of silicon photonics, from driver electronics to receiver electronics.

Figure 1 shows the chain. Electrical data enters a driver, which swings a voltage on the modulator. The modulator sits in the path of a continuous-wave (CW) laser beam and imprints the data on it. The modulated beam travels through waveguides on the chip, couples into optical fiber, crosses whatever distance the system needs, and lands on a photodetector. A transimpedance amplifier (TIA) converts the detector’s tiny current into a voltage the receiving logic can slice into ones and zeros.

The architecture’s defining property is that the laser is separate from the data. The laser runs continuously; the modulator is the only element switching at data rate. That is different from the directly modulated lasers used in short-reach optical links, where the laser current itself is toggled. Separating the roles lets designers optimize the laser for power, stability and wavelength accuracy, and the modulator for speed and linearity.

Waveguides: Wires Made of Index Contrast

A waveguide in SOI is a ridge of silicon, commonly in the neighborhood of 220 nanometers thick and about 400 to 500 nanometers wide for single-mode operation near the 1310 nm and 1550 nm telecom wavelengths. Silicon’s refractive index is about 3.5 and silicon dioxide’s is about 1.45. That large contrast traps light in the ridge by total internal reflection and lets it follow bends with radii of a few microns. This is why optical circuits can be dense: a bend that would leak badly in a glass fiber works fine in silicon.

Propagation loss in a well-made strip waveguide is typically on the order of a few decibels per centimeter, and lower for wider rib waveguides or silicon nitride. Because on-chip paths are millimeters, not meters, that is acceptable. The expensive losses live elsewhere, at the interfaces, which we return to in the coupling section.

Waveguides are also the tool for building passive structures: splitters, couplers, interferometers, and the grating-based filters used for wavelength multiplexing. A directional coupler, for example, brings two waveguides within a few hundred nanometers so their evanescent fields overlap and power transfers between them. Control the gap and the length and you set the split ratio. That is how a Mach-Zehnder modulator divides and recombines a beam, and how a microring picks light off a bus waveguide.

Photodetectors: Germanium on Silicon

Silicon is transparent at 1310 and 1550 nm because photons at those wavelengths carry less energy than silicon’s bandgap. Detecting them requires a material that absorbs there. Germanium, grown epitaxially on silicon and integrated in the same foundry flow, does the job. A germanium photodiode absorbs near-infrared light, creating electron-hole pairs that a reverse bias sweeps out as photocurrent. Foundry germanium detectors reach tens of gigahertz of bandwidth with responsivity around the order of one ampere per watt, which is enough that the receiver’s noise performance is set mostly by the TIA rather than the diode.

The detector side is where silicon photonics is the least controversial. The hard engineering is on the transmit side: getting a light source and a fast, efficient modulator onto silicon.

Why the Laser Does Not Live in the Silicon

Silicon has an indirect bandgap. An excited electron needs a simultaneous change in crystal momentum to recombine with a hole and emit a photon, which makes spontaneous emission slow and lasing impractical. Practical lasers for silicon photonics therefore use direct-bandgap III-V compound semiconductors such as indium phosphide (InP) or gallium arsenide-based quantum-dot structures. There are three ways to get that gain material next to the silicon:

1. Heterogeneous bonding. III-V material is wafer- or die-bonded onto the SOI wafer and processed into a laser that couples directly to a silicon waveguide. This puts the laser on the chip but ties laser yield and reliability to the photonic die.
2. Flip-chip or hybrid attachment. A finished laser die is placed on the photonic chip and aligned to a waveguide facet or an etched cavity. This allows testing the laser before assembly, at the cost of precise placement.
3. External laser source. The laser lives off-chip, often in a separate pluggable or field-replaceable module, and delivers CW light through polarization-maintaining fiber to the photonic chip.

The third option is the pivot of the CPO era, and we will see why when we reach laser reliability. The short version is that lasers are the least reliable and hottest element in the system, so you want to be able to swap them without scrapping a switch.

Deeper Analysis: Modulators, Wavelengths and Fabrication

Mach-Zehnder Modulators: Interference as a Switch

A Mach-Zehnder modulator (MZM) splits an incoming beam into two arms, applies a voltage-controlled phase shift to one or both, and recombines them. If the arms arrive in phase, the output is bright. If they arrive half a wave (pi radians) apart, the waves cancel and the output goes dark. The modulator never creates or destroys light as such; it steers it between a recombined output and a radiated or rejected port.

Silicon has no linear electro-optic (Pockels) effect, so the phase shift is produced by the plasma dispersion effect: changing the density of free carriers in the waveguide changes its refractive index and absorption. In a carrier-depletion modulator, a reverse-biased PN junction runs along the waveguide, and the applied voltage widens or narrows the depletion region, changing the carrier population overlapping the optical mode. This is fast, since depletion needs no slow carrier injection, but the index change per volt is small. Typical silicon depletion modulators have a voltage-length product (V-pi-L) on the order of 1 to 3 V-cm in published literature, meaning a millimeter-scale phase shifter needs multiple volts to reach pi. That is why MZMs are long (often 1 to several millimeters) and use traveling-wave electrodes with termination resistors, driven by dedicated RF drivers.

A short worked example (illustrative, not a specific product): if V-pi-L is 2 V-cm and the arm is 3 mm (0.3 cm) long, V-pi is about 6.7 V for a single-arm drive. Push-pull drive on both arms halves that, to roughly 3.3 V, which is still above what a modern low-voltage CMOS output can supply directly. Real designs combine segmented electrodes, optimized doping and drivers fabricated in a more tolerant technology, trading area and energy for swing.

MZMs have two big advantages. Their response is broadband, so they tolerate laser wavelength drift and temperature changes better than resonant devices. And the transfer function is well suited to multi-level signaling such as PAM4 (4-level pulse amplitude modulation), which modern 200 Gb/s-per-lane links rely on. Their disadvantages are area and drive energy: a long phase shifter driven by multi-volt swings costs more picojoules per bit than a compact resonant device.

Microring Modulators: Small, Efficient, and Fussy

A microring modulator is a tiny circular waveguide, typically a few microns to ten microns in radius, placed next to a bus waveguide. At wavelengths that fit a whole number of times around the ring, light builds up in the ring and is removed from the bus. At other wavelengths it passes. A small change in the ring’s refractive index shifts its resonance, moving the notch on or off the laser wavelength and thereby modulating the transmitted power.

Because light circulates many times, the ring needs a far smaller index change than an MZM, so it can be a few microns across and consume very little drive energy. Published research and vendor materials report energy per bit in the tens of femtojoules per bit range for ring-based links, against hundreds of femtojoules or more for MZM drivers; treat exact figures as device- and design-specific. The ring also acts as a wavelength filter, which is the property that makes it ideal for wavelength-division multiplexing: a cascade of rings of slightly different sizes on a single bus can each modulate its own wavelength.

The price is sensitivity. A silicon ring’s resonance moves about 70 to 80 picometers per kelvin near 1550 nm, a figure that follows from silicon’s thermo-optic coefficient of roughly 1.8 x 10^-4 per kelvin. A ring with a resonance linewidth of about 100 picometers can be pushed off the laser line by a temperature change of roughly one to two degrees. Practical designs therefore add a micro-heater and a control loop per ring, which we revisit in the failure-modes section.

Figure 2: Mach-Zehnder (split, phase-shift, recombine) versus microring (resonant notch on a bus waveguide) modulators.

Figure 2 shows the two structures side by side. The Mach-Zehnder is a path-length trick, the ring a resonance trick. Other modulator families compete at the edges. Germanium-silicon electro-absorption modulators (EAMs) use the Franz-Keldysh effect to change absorption with field, and some reviews report energy figures as low as single-digit femtojoules per bit in lab devices. Thin-film lithium niobate offers a true Pockels effect with very low V-pi and high bandwidth, at the cost of a less CMOS-native process. Plasmonic and polymer hybrids aim for even higher speed. I treat these as promising but not yet the volume default in AI switches.

Wavelength-Division Multiplexing: Capacity from Color

A single optical carrier at 200 Gb/s is impressive, but fiber and waveguide bandwidth are vastly larger than any one modulator’s. Wavelength-division multiplexing (WDM) places several laser wavelengths in the same waveguide or fiber, each carrying its own modulated data stream. A passive multiplexer combines them at the transmitter and a demultiplexer separates them at the receiver.

Two flavors matter here. Coarse WDM (CWDM) uses widely spaced channels (20 nm apart in the standard grid) with relaxed filter and laser-tolerance requirements, suited to low-cost links. Dense WDM (DWDM) spaces channels tens to hundreds of gigahertz apart, packing many carriers into a fiber, and demands tight wavelength control. Optical I/O chiplets such as Ayar Labs’ TeraPHY use DWDM-style dense channels fed by an external multi-wavelength light source, which is why the capacity of one fiber can exceed what a single-wavelength link could carry.

Here is the arithmetic, using Ayar Labs’ published numbers for its UCIe optical chiplet: 8 Tb/s of bandwidth over 16 wavelengths implies an average of 500 Gb/s per wavelength (an illustrative division of the vendor’s two figures, not a stated per-wavelength rate). The point is that adding wavelengths scales bandwidth without adding fibers or waveguides, so the physical pin count and beachfront (edge length) problem eases.

Fabrication: Reusing the CMOS Fab

Making photonic devices on SOI uses lithography, etch, implant, epitaxy and metallization steps that a CMOS fab already runs. Waveguide patterning is demanding because sidewall roughness scatters light; a few nanometers of roughness matter, and 193 nm immersion lithography with careful etch control is the norm. Implant steps form the PN junctions in modulators, germanium epitaxy forms detectors, and standard metal layers route RF signals. Modern foundry flows also add silicon nitride layers for lower-loss waveguides and edge couplers, plus deep trenches or V-grooves for fiber attachment.

The consequence for cost is subtle. The wafer processing is cheap; the packaging and test are not. A photonic die needs optical alignment with sub-micron tolerance, laser attach, fiber attach and optical testing, and none of that is as automated as electrical wire bonding. Much of the industry’s capital in 2026 is being spent making optical packaging look like semiconductor packaging, and TSMC’s COUPE effort is the clearest expression of that goal.

Co-Packaged Optics: Bringing the Light to the Chip

In a pluggable design, the switch ASIC drives a high-speed electrical signal across the printed circuit board, through a connector, into a transceiver at the faceplate, where a digital signal processor (DSP) cleans it up and drives the optics. At 200 Gb/s per lane that electrical path is a serious burden: the board trace loses signal, so the ASIC needs powerful SerDes (serializer/deserializer) circuits to push it, and the module needs a DSP to recover it. Much of the power in a pluggable link goes into overcoming that electrical channel, not into the light.

Co-packaged optics shortens the channel to millimeters. The optical engines sit on the same package substrate as the switch die, connected by short, low-loss traces or through advanced packaging. The SerDes can be a lighter, shorter-reach design, and in some architectures the retimer or DSP can be removed entirely. Fewer power-hungry electrical stages, fewer connectors and fewer separate modules are the whole thesis.

Figure 3: The electrical path from ASIC to optics in a pluggable design versus a co-packaged design.

Figure 3 contrasts the two. The long electrical channel on the left is where the energy goes; the CPO layout on the right replaces it with a short package-level hop and moves the fiber interface to the package edge or front panel.

The Energy Arithmetic

Use round, illustrative numbers to see why this matters. Suppose a 102.4 Tb/s switch were fully loaded. At 15 picojoules per bit (a figure commonly quoted for pluggable optical links in vendor and press discussions), the optical interconnect would draw about 1,536 watts (102.4 x 10^12 bits per second x 15 x 10^-12 joules per bit). At 5 picojoules per bit, the same traffic costs about 512 watts. Across a cluster with thousands of such switches, a roughly 1 kW saving per switch is the difference between a manageable cooling plan and an overbuilt one, and every watt saved on interconnect is a watt available for compute under a fixed facility power cap. For the facility-level context, see our analysis of AI data center power, grid and nuclear supply.

These are not product measurements. They show the structure of the argument: power scales linearly with energy per bit, and at multi-terabit aggregate rates even single-digit picojoule differences become kilowatts. Vendors quote their own ratios, covered next, and you should evaluate them on the same basis: what is included in the picojoules-per-bit figure (laser? DSP? drivers?) and at what temperature and loading.

Where the Industry Stands in 2026

NVIDIA. In its March 2025 announcement, NVIDIA introduced two CPO switch families: Quantum-X Photonics for InfiniBand and Spectrum-X Photonics for Ethernet. According to NVIDIA’s press release, Quantum-X offers 144 ports of 800 Gb/s, built on 200 Gb/s SerDes, with liquid cooling for the on-package photonics. Spectrum-X configurations were described at 128 ports of 800 Gb/s (about 100 Tb/s) and 512 ports of 800 Gb/s (about 400 Tb/s). NVIDIA claims, against traditional pluggable approaches, 3.5x better power efficiency, 4x fewer lasers, 63x greater signal integrity and 10x better network resiliency at scale. Those are vendor claims that I have not seen independently verified, and the exact multipliers have varied between NVIDIA communications over time. The release lists TSMC, Coherent, Corning, Foxconn, Lumentum and SENKO among joint development partners.

Broadcom. Broadcom has shipped a sequence of CPO generations. Its Tomahawk 6-Davisson (TH6-Davisson) is described in launch coverage as a 102.4 Tb/s Ethernet switch with 16 optical engines of 6.4 Tb/s each integrated on the package, 200 Gb/s per channel, field-replaceable ELSFP laser modules and an approximate 70 percent reduction in optical interconnect power relative to pluggables (Broadcom’s claim). The arithmetic is consistent: 16 engines x 6.4 Tb/s equals 102.4 Tb/s, and 6.4 Tb/s at 200 Gb/s per channel means 32 channels per engine. Broadcom says a fourth-generation platform at 400 Gb/s per channel is in development; that is a roadmap statement, not a product.

TSMC COUPE. TSMC’s Compact Universal Photonic Engine stacks an electronic die on a photonic die using its SoIC-X bonding, aiming for very short, dense electrical connections between the electronic IC and the photonic IC. TSMC has described a roadmap in stages: a first generation as an on-substrate engine in the 1.6 Tb/s class, then integration with CoWoS packaging at the interposer level for higher aggregate bandwidth, and finally integration closer to the processor package. Reported targets for later generations (6.4 Tb/s and 12.8 Tb/s) come from trade-press coverage of TSMC presentations, so check TSMC’s own material for current numbers before relying on them. TSMC’s role matters because it ties photonics to the same advanced-packaging capacity that AI accelerators already compete for. For that supply-side picture, see our look at the TSMC 2nm and AI chip competition.

Ayar Labs. Ayar Labs focuses on optical I/O chiplets rather than switch faceplates. Its TeraPHY chiplet is described by Inside HPC’s coverage as the first optical UCIe (Universal Chiplet Interconnect Express) chiplet, delivering 8 Tb/s with 16 wavelengths from the company’s SuperNova multi-wavelength light source, with supporting statements from AMD, Alphawave Semi, d-Matrix and GlobalFoundries. The idea is that an accelerator package can speak UCIe to a nearby optical chiplet, which turns the die edge into a fiber port. That is conceptually the CPO idea pushed from the switch to the XPU.

Lightmatter. Lightmatter positions its Passage line as a photonic interposer that lets multiple chiplets communicate optically across a large surface rather than only at the edge. I do not cite specific Passage bandwidth numbers here because I could not verify current published figures; check Lightmatter’s own documentation for specifications and availability.

The pattern across vendors is consistent. Everyone agrees that the electrical channel is the problem. They differ on where the optical engine sits (switch package, interposer, chiplet at the accelerator edge), on the laser strategy, and on how much of the DSP can be removed.

Laser Strategy: Why External and Pluggable Light Sources Won

Early CPO prototypes often put lasers inside the package with the optical engine. The trouble is that lasers are the least reliable element: their output degrades with time and temperature, and a failing laser in a bonded package means a failed switch. The 2025-2026 products converge on external laser sources. Broadcom’s field-replaceable ELSFP modules are an example of this serviceability principle, and NVIDIA’s claim of four times fewer lasers hints at a design with a few high-power CW lasers feeding many modulators rather than one laser per channel.

The mechanism makes sense. A CW laser can be split by waveguides into many branches, each feeding a modulator, so a single high-power laser can serve many channels. The trade is optical power budget: splitting divides power, and each coupling and modulator insertion loses more. Designers need laser power high enough to deliver adequate optical modulation amplitude at the receiver after every split and loss, yet low enough to stay within eye-safety limits at the fiber connectors and thermal limits in the package. Figure 4 sketches the system view.

Figure 4: A CPO system with a serviceable external laser source, on-package optical engines and a thermal control loop.

Power and Bandwidth Trade-offs at a Glance

Dimension	Pluggable optics	Co-packaged optics	Optical I/O chiplet
Electrical channel length	Long (board plus connector)	Short (package)	Very short (die edge)
Serviceability	Hot-swap modules	Laser swappable, engine fixed	Engine fixed to package
Typical position	Switch faceplate	Switch package	XPU or memory package
Power per bit (vendor claims)	Highest	Reported 3.5x to ~70 percent savings	Targeted lowest
Thermal coupling	Isolated from ASIC	Shares package heat	Shares package heat
Maturity in 2026	Mass volume	Early production	Sampling and early adoption

The pivotal row is thermal coupling. A pluggable module is thermally separate from the ASIC; a CPO engine lives millimeters from a hundreds-of-watts die, which turns thermal control from a convenience into a requirement.

Trade-offs, Gotchas, and What Goes Wrong

Thermal drift. Rings and wavelength filters shift roughly 70 to 80 picometers per kelvin in silicon. A switch ASIC whose load changes in milliseconds creates a moving thermal environment. Designs counter this with per-ring heaters and feedback that monitors a tap of the light, typically an on-chip photodiode watching the ring’s transmitted power or a pilot tone. The costs are real: heater power adds to energy per bit, control loops need calibration at startup and can lose lock during fast transients, and a ring that loses lock stops carrying data. MZMs are more thermally tolerant but still need bias control to hold the quadrature point.

Coupling and insertion loss. A silicon waveguide is sub-micron; a single-mode fiber core is about 9 microns. Matching these modes needs an edge coupler with a spot-size converter or a grating coupler, with loss typically budgeted at around 1 to 3 dB per interface in practice. Add multiple interfaces and a splitter tree and the optical budget evaporates quickly. Fiber attach is also a yield risk: a misaligned fiber array on a package that has already absorbed a switch ASIC is expensive to rework.

Laser reliability and eye safety. CW lasers fail by gradual power decline or abrupt facet damage. External laser modules reduce the blast radius, but now the system must monitor optical power and calibrate for slow degradation. High-power CW light at connectors also demands interlocks or power limits.

Serviceability and blast radius. If the optical engine is integrated into the switch package, a failed engine can mean replacing the whole switch or a large board. Pluggable optics have a simple operational story: swap the module. CPO moves failure handling from field-replaceable modules to design margin, redundancy and software that routes around failing links. Operators accustomed to pluggable ecosystems must plan spares and RMA flows differently.

Test and ecosystem lock-in. Pluggable transceivers are multi-vendor and standardized (IEEE 802.3 families, MSA specifications). CPO products are tightly integrated, and mixing optical engines from one vendor with switches from another remains the exception. Standards work on CPO interoperability is ongoing, and I would treat multi-vendor interoperability as an unproven assumption for now.

Fiber management. Fewer lasers does not mean fewer fibers. High-radix CPO switches expose many fibers at the faceplate, and fiber ribbons, shuffles and patching become physical design problems of their own.

Over-reading vendor numbers. Statements such as “3.5x better power efficiency” compare against a baseline the vendor chooses. Ask whether the baseline includes DSP-based pluggables or linear pluggable optics (LPO) that remove the DSP, and whether the CPO figure includes the external laser and its cooling.

Practical Recommendations

For a platform or network engineer, the useful question is not whether optics will win, but where in your stack it pays first. Scale-out Ethernet and InfiniBand fabrics for GPU clusters are the first CPO target because switch radix and power are the immediate constraints. Scale-up domains (the tightly coupled accelerator groups inside a rack or pod) are the next battleground, where optical I/O chiplets compete with copper backplanes. For memory-bound inference, optical links are also being explored to widen the path between compute and memory; our discussion of the memory wall and optical interconnect places that in context.

When evaluating a silicon photonics product, force the vendor to be specific about the following.

• Define the pJ/bit boundary. Does the number include laser wall-plug power, thermal tuning, drivers and TIAs, or only the modulator?
• Check the baseline. Compare against the pluggable generation you would actually buy, including linear-drive options, not a strawman.
• Ask about laser serviceability. Where is the laser, what is its field-replacement procedure, and how is degradation monitored?
• Examine thermal design. What is the heater power per channel, the control-loop recovery time after load steps, and the specified coolant temperature?
• Plan the failure domain. How many ports go down if one optical engine fails, and does your topology tolerate it?
• Test fiber logistics. Prototype the cabling plant; do not assume it scales trivially.
• Verify standards compliance. Confirm which IEEE 802.3 or OIF specifications are met, and what interoperability has actually been demonstrated.

For learners, a productive path is to model a single link budget in a spreadsheet: laser power, split loss, modulator insertion loss, extinction ratio penalty, coupling loss, fiber loss and receiver sensitivity. One afternoon of that exercise teaches more than reading three press releases.

Frequently Asked Questions

How do silicon photonics chips work in simple terms?

A laser supplies a steady beam of infrared light. Waveguides etched in silicon carry it to a modulator, which switches the light’s brightness or phase according to electrical data. The modulated light travels through fiber to a photodetector, usually germanium on silicon, which converts it back to electrical current. The whole chain except the laser is built with standard chip fabrication techniques on silicon-on-insulator wafers.

Why can silicon not emit light, and how is that solved?

Silicon has an indirect bandgap, so electrons and holes recombine mostly by producing heat or lattice vibrations rather than photons, which makes efficient lasing impractical. Designers attach direct-bandgap III-V materials such as indium phosphide, either bonded to the wafer, flip-chipped as a separate die, or located in an external laser module that sends continuous light to the chip over fiber.

What is the difference between a Mach-Zehnder and a microring modulator?

A Mach-Zehnder modulator splits light into two arms, shifts the phase in one, and recombines them so interference switches the output. It is broadband and temperature tolerant but long and drive-hungry. A microring modulator shifts a resonance on or off the laser wavelength. It is tiny and efficient but highly temperature sensitive and typically needs a heater and control loop.

What is co-packaged optics and why does it matter for AI?

Co-packaged optics places the optical engine on the same package substrate as the switch or processor, shortening the electrical path from board scale to millimeters. That reduces the power spent on high-speed electrical signaling and retiming. For AI clusters, which are limited by interconnect power and radix, vendors claim large efficiency gains, though those figures are vendor-reported and baseline-dependent.

Is silicon photonics replacing copper entirely?

No. Copper remains cheaper and simpler for very short links, and passive copper cables still connect devices within a rack where reach allows. Optics is taking over where distance and speed make copper’s loss and power costs unacceptable, starting with switch-to-switch links and moving closer to the accelerator. Expect a long period where copper, pluggable optics, CPO and optical I/O coexist.

What are the biggest risks of adopting co-packaged optics?

The main risks are serviceability, thermal control and ecosystem lock-in. A failed on-package optical engine is harder to replace than a pluggable module, rings and filters need active temperature stabilization next to a hot ASIC, and multi-vendor interoperability is immature. Mitigate by choosing designs with replaceable external lasers, testing failure behavior, and planning topology redundancy before scale deployment.

Further Reading

• Silicon photonics and co-packaged optics in the data center for deployment economics.
• Memory wall, optical interconnect and LPDDR6 for physical AI for the compute-to-memory angle.
• AI data center power, grid and nuclear analysis for facility power constraints.
• TSMC 2nm and the AI chip race for packaging and foundry context.
• External: NVIDIA Quantum-X and Spectrum-X Photonics announcement and Ayar Labs TeraPHY UCIe optical chiplet coverage.

By Riju — about