800V DC Data Center Power: Solid-State Transformers, Rack Architecture and Efficiency Math (2026)

A rack in a classic enterprise data center drew perhaps 5 to 10 kilowatts. The racks NVIDIA calls AI factory building blocks already exceed 100 kW, and the vendor’s roadmap points at 1 MW per rack. At that scale the arithmetic of low-voltage distribution turns hostile: at 54 volts, one megawatt is about 18,500 amps, and the copper needed to carry it starts to crowd out the computers it feeds. The proposed escape is an 800V DC data center: convert medium-voltage grid power to roughly 800 volts direct current once, near the building edge, and distribute that DC all the way to the rack.

This matters now because the specification work has moved from slideware to standards. The Open Compute Project (OCP) published a final Mt. Diablo disaggregated power rack specification in October 2026, semiconductor and switchgear vendors are announcing solid-state transformer (SST) programs, and NVIDIA has tied full-scale 800 VDC production to its Kyber rack generation in 2027.

You will leave with the physics behind the voltage choice, a worked and clearly labelled efficiency calculation, a mental model of how an SST is built, and an honest list of what is still unsolved: protection, arc flash, storage, standards and timelines.

What this covers: why 54 V busbars and the AC conversion chain hit limits, the 800 VDC reference architecture, SST topology and SiC devices, protection and battery design, liquid-cooling coupling, grid interconnect, and the uncertainties that remain.

Context and Background

For about two decades the dominant hyperscale power chain has been: medium-voltage AC from the utility, a step-down transformer to 415/480 VAC, a double-conversion uninterruptible power supply (UPS), power distribution units and busways, and then, inside each rack, power supplies that rectify AC to 48 to 54 V DC for a rack busbar. A last stage of board-level DC-DC converters takes that down to 12 V and finally to the roughly one volt a GPU core needs. NVIDIA’s own description of the current design says racks use 54 VDC distribution with bulky copper busbars carrying power from rack-mounted power shelves to compute trays, and that this design hits physical limits as racks exceed 200 kW (NVIDIA Technical Blog).

Higher-voltage DC is not a new idea. Telecom has run 48 V DC for a century, and several vendors piloted 380 VDC data center distribution in the 2010s. Those pilots never took over, in part because AC server power supplies were cheap, ubiquitous and certified, and in part because DC protection hardware was immature. What changed is the load. A GPU rack that behaves like a small industrial plant makes the conversion chain a first-order cost, and the electric-vehicle industry has since industrialised exactly the parts that were missing: silicon carbide (SiC) and gallium nitride (GaN) power devices, high-voltage DC connectors, and fast DC protection.

Two voltage families are now in play. NVIDIA proposes a single 800 VDC distribution (two conductors). Google, Meta and Microsoft, working through OCP’s Mt. Diablo effort, specify a primary output of plus and minus 400 VDC with a common return, with an 800 VDC differential option (OCP Mt. Diablo v1.0.0). They are electrically close cousins: a plus/minus 400 V system has 800 V between its outer conductors. The argument is partly about grounding and partly about which silicon and connector ecosystem wins.

If your interest is the upstream half of the problem, where the megawatts come from before they reach the hall, our post on behind-the-meter power, nuclear PPAs and AI data center architecture covers the supply side. This post covers what happens after the utility meter.

Why 54V Busbars and the AC Chain Hit a Wall

Direct answer: At 54 V a 1 MW rack needs roughly 18,500 A, and resistive loss scales with the square of current, so copper mass, heat and rack volume explode. The legacy chain also stacks four or five conversion stages, each losing a few percent. Raising distribution to 800 V cuts current by about 15 times and removes most stages.

Figure 1: The legacy chain. Power is converted or transformed at nearly every box between the grid and the GPU, and the final 54 V hop carries enormous current.

Figure 1 shows the incumbent path. Read it left to right and count the transformations: MV to LV transformer, AC to DC to AC inside the UPS (in double-conversion mode), AC to DC in the rack power shelf, and DC to DC on the board, with several more steps hidden inside the GPU tray. Each stage has its own efficiency, its own heat output, its own fan and its own failure rate. The figure also shows where current is highest: the last two hops, which run at the lowest voltage.

The current problem: I = P / V

Power equals voltage times current, so for a fixed load the current is inversely proportional to voltage. For a 1 MW rack (an illustrative round figure, which matches the Kyber-class target NVIDIA describes), the distribution current at different bus voltages is:

Bus voltage	Current for 1 MW	Relative to 54 V
54 V DC	about 18,500 A	1.0x
400 V DC	2,500 A	0.135x
800 V DC	1,250 A	0.068x

These are straight arithmetic, ignoring conversion losses and power factor. Conductor loss is I squared times R. For an identical conductor, dropping current to 6.8% of its original value drops resistive loss to about 0.46% of the original, a factor of roughly 219. In practice you do not keep the conductor the same size; you shrink it, trading some of that loss reduction for copper savings. NVIDIA states that a 1 MW rack at 54 VDC would need up to 200 kg of copper busbar, and that a 1 GW facility could require up to 200,000 kg of rack busbar copper; it also says 800 V busways carry 85% more power through the same conductor size and cut copper by 45% compared with 415 VAC at row level. Those are the vendor’s figures and I have not independently reproduced them, but the direction is physically unambiguous.

The space problem

Power shelves are not free. NVIDIA reports that GB200 NVL72 and GB300 NVL72 racks use up to eight power shelves, and that at megawatt scale a 54 V design would need up to 64 U of rack space for power shelves alone. A standard rack offers roughly 42 to 48 U. In other words, at 1 MW the power conversion would not fit inside the rack that is supposed to hold the compute. The only options are to move conversion outside the rack (a “sidecar” or a separate power rack, which is exactly what both NVIDIA and the OCP specification do) or to raise the distribution voltage so the in-rack conversion shrinks to an isolated DC-DC stage.

The conversion chain problem

Efficiency compounds multiplicatively. A chain of stages with efficiencies e1, e2, … en delivers the product of them. The following numbers are illustrative only, chosen to be in a plausible range for modern equipment and not taken from any vendor datasheet:

Stage (legacy chain)	Illustrative efficiency
MV to 415 V transformer	99.0%
Double-conversion UPS	96.0%
PDU and busway	99.5%
Rack PSU, AC to 54 V	96.0%
54 V busbar and connectors	99.0%
Board DC-DC, 54 V to point of load	97.0%

The product is 0.990 x 0.960 x 0.995 x 0.960 x 0.990 x 0.970, which is about 0.872. So roughly 12.8% of grid energy becomes heat before the GPU does any work, in this illustrative chain. For a 100 MW campus that is about 12.8 MW of heat to remove, and that heat is produced in many places, some inside the IT rack where cooling is already stretched.

A simplified 800 VDC chain replaces the transformer, UPS and rack PSU with a single MV-to-DC stage, then distributes DC and finishes with an isolated DC-DC stage in the rack:

Stage (800 VDC chain)	Illustrative efficiency
MV AC to 800 VDC (SST or rectifier)	98.0%
DC distribution and protection	99.5%
Rack DC-DC, 800 V to 54 V or 12 V	97.5%
Board DC-DC to point of load	97.0%

The product is 0.980 x 0.995 x 0.975 x 0.970, about 0.922. The improvement of roughly five percentage points is in the same neighbourhood as the “up to 5%” end-to-end efficiency gain NVIDIA claims over 54 V systems, but treat my arithmetic as a demonstration of the mechanism, not a prediction. The result is highly sensitive to the first stage: if the MV-to-DC conversion delivers 97% rather than 98%, you lose about a point of the gain, which is why SST efficiency (covered below) is the make-or-break number.

The efficiency story has a second half that is easy to miss. Fewer stages mean fewer fans and fewer power supplies, and NVIDIA argues this reduces component count and the maintenance load from failed rack PSUs, claiming up to 70% lower maintenance cost and up to 30% lower total cost of ownership. These are marketing-grade numbers from the architecture’s sponsor, so read them as the upper bound of a credible range rather than a planning input.

The 800 VDC Reference Architecture, Stage by Stage

Direct answer: An 800 VDC facility converts 13.8 kV AC grid power to 800 V DC once at the building perimeter, runs DC busways to the rows, and places only an isolated DC-DC converter in or beside each rack. Energy storage sits on the DC bus. The UPS, the low-voltage transformer and the per-rack AC rectifier all disappear.

Figure 2: The 800 VDC path. One MV-to-DC conversion at the edge, protected DC distribution, then isolated DC-DC at the rack and a point-of-load stage on the board.

Figure 2 should be read as a mirror of Figure 1 with the middle hollowed out. NVIDIA describes the grid-to-power-room step as converting 13.8 kV AC directly to 800 VDC at the data center perimeter using industrial-grade rectifiers, which “removes most intermediate conversion steps.” Row-level distribution then uses 800 V busways, racks take a two-conductor 800 V feed, and the in-rack path runs 800 V to 54 V or 12 V and then to core voltage. The same blog says full-scale production of 800 VDC data centers is expected to coincide with Kyber rack-scale systems in 2027, and that at GTC 2025 NVIDIA showed an 800 V sidecar powering 576 Rubin Ultra GPUs in a single Kyber rack.

What each component is, why it exists, and where it sits

The perimeter converter (what, where). This is the box that takes MV AC and produces regulated DC. It can be a conventional transformer plus a rectifier line-up (the “industrial-grade rectifier” path), or a solid-state transformer. Its job is to be the only large AC-to-DC conversion in the site. Because it is the biggest single efficiency lever and the biggest single point of failure, it is almost always modular and N+1 or better. It sits at the power room, between the utility yard and the data hall.

The DC bus with storage (why). A conventional UPS exists to bridge utility outages and, with generators, to carry the load until backup power starts. In a DC design that duty moves to batteries or capacitors attached to the DC bus through DC-DC converters. NVIDIA says energy storage is part of the architecture to manage load spikes and subsecond GPU power fluctuations and that more detail will follow. Section on batteries below covers the engineering.

Protection at three boundaries (how). NVIDIA lists overcurrent protection at the power room to hall boundary, the hall to row boundary, and the row to rack level, with options including fuse-and-disconnect combinations, emerging solid-state devices and safety breakers, and it is candid that protection reliability still needs innovation. That candour is justified, as the protection section explains.

800 V busways (where). A busway is an enclosed set of bus conductors that runs overhead or under floor and feeds racks through tap-off units. The 800 V DC variant has two conductors instead of three phases plus neutral, no reactive-power flow and no skin effect, which is why NVIDIA reports 85% more power through the same conductor size relative to 415 VAC.

The rack-side DC-DC stage (how). This is an isolated converter that steps 800 V to 54 V or 12 V. It is far simpler than an AC-DC supply: no power-factor correction stage, no rectifier bridge, no large bulk capacitors for 50/60 Hz ripple. That simplicity is a major source of the claimed reduction in part count. Isolation is non-negotiable because it keeps the 800 V distribution galvanically separate from the chassis-referenced low-voltage domain that technicians and servers touch.

The OCP Mt. Diablo alternative: the sidecar

The OCP final specification, effective October 8, 2026 and authored by Microsoft, Meta and Google, defines a disaggregated “power rack,” a sidecar next to the IT rack. It delivers plus/minus 400 VDC (regulated to plus or minus 0.5%) with an optional 800 VDC differential mode in which the return is safety-isolated from protective earth. Its numbers are worth knowing because they are concrete:

Target power is roughly 800 kW to 1.1 MW or more per power rack, with paralleling and current sharing between racks.
Hot-swappable 1OU power supplies are each rated roughly 25 to 30 kW depending on input voltage, in shelves up to 2OU.
Battery backup units give 45 to 90 seconds of holdup at full load, and capacitor bank units are an alternative; without any storage the supplies ride through only about 20 ms.
A concealed, air-cooled vertical three-conductor busbar is rated up to 1.1 MW.
Output cables are rated 50 kW (63 A) or 100 kW (125 A), with a voltage drop limit of 0.1% at 5 m, and overcurrent protection is required on all outputs.
End-to-end efficiency is specified from more than 95% up to 98% depending on load and input voltage.

Notice what this design is and is not. The sidecar still takes AC input (415/480 V, or 400 V) and rectifies it, so it improves the last-meter distribution and rack density, but it keeps an AC-DC stage inside the building. NVIDIA’s end state moves that rectification out to the perimeter. The two are best seen as stages on a migration path rather than opposing camps, and a facility could adopt a sidecar now and swap the AC feed for an MVDC or 800 V feed later.

For the compute side, the density that forces all this is covered in our post on GPU sharing in Kubernetes with MIG, MPS, time slicing and vGPU; partitioning raises utilisation, and higher utilisation means a more sharply varying and higher average power draw on exactly the bus we are designing.

Solid-State Transformers: Topology, Devices and Efficiency

Direct answer: A solid-state transformer replaces the iron-core 50/60 Hz transformer and rectifier with power electronics: an AC-DC front end, a high-frequency inverter driving a small isolating transformer, and a rectifier output. Silicon carbide devices make the high switching frequency and medium voltage practical, shrinking size and enabling direct MV-to-800 V DC conversion.

Figure 3: A modular SST. A controller coordinates an AC front end, an MV DC link, a high-frequency isolation stage and a DC output rectifier.

How an SST works

A conventional transformer works at line frequency, so its core and windings are large: size scales inversely with frequency for a given power. An SST first rectifies the MV AC into a DC link, then chops that DC at tens of kilohertz (the exact frequency is a design choice and I will not quote a specific one), passes it through a compact high-frequency transformer that provides galvanic isolation, and rectifies again to the desired DC output voltage. Because a single semiconductor cannot withstand 13.8 kV, practical SSTs use many cells in series on the input side and in parallel on the output side, in a modular multilevel arrangement, which is the reason Figure 3 is drawn as a modular stack with a shared controller.

Two properties make SSTs attractive for an 800 VDC site. First, they can output DC directly, so the data center needs no separate rectifier line-up and no LV transformer. Second, they are controllable: they can regulate output voltage, limit fault current in microseconds, and in principle provide reactive-power support to the grid. A line-frequency transformer does none of these; it just passes through whatever the grid and load do to each other.

What has actually been announced

Public vendor claims are the best evidence available, and they should be read as claims. In November 2025, SolarEdge and Infineon announced a joint SST development effort for AI data centers: a modular system taking 13.8 to 34.5 kV medium-voltage input and producing 800 to 1500 V DC, at 2 to 5 MW per modular system, with an efficiency target above 99%. The article describing it notes that the platform was still in development, with no deployment partners or commercialisation timeline named (eeNews Europe). A “target above 99%” is a design goal, not a measured result.

In October 2026, Infineon and Eaton announced that Infineon would supply SiC power devices for Eaton’s medium-voltage SST (MVSST 2.0) platform aimed at 800 VDC AI data center architectures, and that the two were studying a next-generation platform based on 2.3 kV and 3.3 kV SiC modules, with no measured efficiency figures or timeline disclosed (EE Times Japan report). NVIDIA’s own ecosystem list names Eaton, Schneider Electric and Vertiv among data center power systems partners, and a long list of semiconductor suppliers including Infineon, Navitas, onsemi, ROHM, STMicroelectronics and Texas Instruments, among others. Note that NVIDIA says it is studying CapEx, OpEx and safety for both traditional transformer-based designs and SST-based designs; an SST is a candidate, not a mandate.

Why SiC, and where GaN fits

Silicon carbide has a wide bandgap, which gives it a much higher breakdown field than silicon. In practice that means a SiC MOSFET at a given voltage rating can be thinner, with lower on-resistance and far lower switching losses than a silicon IGBT. This is what lets an SST switch at high frequency and still hit high efficiency. The 2.3 kV and 3.3 kV module direction in the Eaton and Infineon work matters because the higher the device voltage, the fewer series cells are needed at 13.8 kV, which reduces part count and control complexity.

Gallium nitride devices are available at lower voltage ratings, with very fast switching and low gate charge, so they fit the downstream, lower-voltage stages: the 800 V to 54 V or 12 V rack converter and the board-level conversion. The usual division of labour in current commentary is SiC for medium and high voltage, GaN for the high-density low-voltage hops, though I could not find a vendor-neutral source that states a definitive boundary, so treat that as a rule of thumb.

The efficiency question is about the comparison, not the headline

A 99% SST sounds better than a 98.5% transformer plus rectifier, but the fair comparison includes the whole chain. A line-frequency MV transformer can itself reach very high efficiency at rated load (illustratively around 99%), and an industrial rectifier adds a stage of its own. The SST wins if its full-chain efficiency, including auxiliary power for gate drivers, cooling and control, at the actual operating load, beats the sum of those stages. Part-load efficiency is often the deciding factor: a data hall rarely sits at nameplate, and AI training loads oscillate. Ask any SST vendor for a curve across 10% to 100% load, and for the number including cooling overhead, before accepting a single headline figure.

Protection, Arc Flash, Storage and Cooling: The Hard Parts

Direct answer: DC is harder to interrupt than AC because current has no natural zero crossing, so faults need fast solid-state or hybrid breakers and careful grounding. Storage must absorb subsecond GPU swings as well as outages. And at megawatt density the power and liquid cooling designs are one coupled system, not two projects.

Figure 4: Three coupled loops. GPU load steps pull the bus down and are caught by capacitors and batteries, branch faults are cleared by solid-state breakers, and the cooling loop sets the heat limit on all of it.

Protection and arc flash

An AC breaker benefits from physics: the current crosses zero 100 or 120 times per second, and an arc that forms while contacts separate will extinguish at one of those crossings if the gap is wide enough. A DC arc has no such help. The inductance of cables and converters stores energy that wants to keep the current flowing, and a sustained DC arc can burn at a steady voltage until something stops it. This is why DC circuit breakers are bulkier for the same rating, use magnetic blowout, arc chutes or capacitor-assisted commutation, and why fuses remain popular for DC.

Fault current at 800 V is also formidable. Available short-circuit current from a large DC source with bus capacitors can rise in microseconds to tens of kiloamps (an illustrative order of magnitude, since it depends on source impedance and capacitance). Because the incident energy in an arc-flash event depends on arc current, voltage and, critically, clearing time, the engineering goal is to shorten clearing time. Solid-state circuit breakers (SSCBs), built from semiconductor switches rather than mechanical contacts, can interrupt in microseconds rather than milliseconds, which is why Infineon and SolarEdge have also been reported to be working on SSCBs for high-voltage DC distribution in AI data centers (per the September 2026 Infineon item that I could only read in summary). The price is on-state loss, since a semiconductor conducts through a finite resistance, and a need for snubbers or varistors to absorb the inductive energy when the switch opens.

Grounding is the less glamorous half. A plus/minus 400 V system can be grounded at the midpoint, solidly or through high resistance. The Mt. Diablo spec allows either, requires ground-fault detection, per-cable residual current detection and overcurrent protection on all outputs, and limits leakage to 3.5 mA AC and 10 mA DC. A high-resistance midpoint ground keeps a single ground fault from tripping the system (continuity of service) but needs detection and a procedure to find and clear the first fault before a second one creates a short. A solid ground trips fast and is simple to reason about, but loses continuity. Neither choice is universal; it should follow the facility’s availability goals.

NVIDIA states that adoption was held back before by technical and deployment issues and that safety, standards and workforce training remain open challenges. I read that as the honest summary: the equipment is arriving faster than electrical codes, inspector familiarity and technician training. Existing frameworks such as the NEC (in the US) and IEC low-voltage rules were written when DC at this power level inside a building was rare; expect pilots to rely on engineered special-case approvals before standard codes catch up. I did not find a verified list of the specific code revisions in progress, so none are claimed here.

Storage: two jobs, two time scales

A UPS battery strings job is to cover the gap until generators start, typically seconds to a few minutes. In an AI cluster there is a second, faster job: synchronous training causes thousands of GPUs to ramp together at the start and end of each compute phase, producing megawatt-scale load swings on timescales of milliseconds to seconds. NVIDIA names these “subsecond GPU power fluctuations” and says storage is built into the architecture to smooth them.

The two jobs want different devices. Capacitors and supercapacitors have enormous power density and nearly unlimited cycles but small energy, so they suit millisecond to second smoothing. Batteries have the energy for minutes of ride-through but degrade with cycling, so using them to smooth every training step wears them out. The OCP spec reflects the split: BBUs for 45 to 90 seconds at full load, capacitor bank units as an option, and a note that without either the supplies hold up only about 20 ms. The BBU also has to meet UL 9540 and 9540A and NFPA 855 for energy storage safety, and the rack must remain stable at up to 10 degrees of tilt.

A worked example makes the sizing concrete. Suppose a 1 MW rack must ride through 60 seconds at full load (illustrative). The energy is 1 MW x 60 s = 60 MJ, or about 16.7 kWh. At a usable depth of discharge of 80% (an assumption) the nameplate battery energy is about 20.8 kWh per rack. For a 100 MW hall of such racks, that is roughly 2 MWh of battery for the same 60 seconds, before derating for end-of-life capacity and temperature. That is a tiny fraction of what a multi-hour grid battery holds, which is why battery fire risk is a safety-compliance problem here, not an energy-capacity problem.

The thing nobody wants is for the grid to see the training oscillation. There is growing attention among utilities and researchers to the power quality effect of large synchronised AI loads, including the need to ride through grid disturbances without tripping. Placing storage on the DC bus, behind the SST, is an architecturally clean way to decouple rack-level swings from the interconnection, and a controllable SST can shape the draw seen by the grid. That is an inference from the topology, not a published performance result.

Liquid cooling coupling

Power and cooling scale together because every watt not delivered to the silicon is a watt of heat. At 1 MW a rack is dominated by direct-to-chip liquid cooling. Google, announcing its plus/minus 400 VDC and 1 MW rack direction at the OCP EMEA Summit, paired it with its fifth-generation Project Deschutes coolant distribution unit, designed for chips above 1,000 W and reporting 99.999% uptime across more than 2,000 TPU pods (Converge Digest). The pairing is deliberate. Moving the AC-DC conversion out of the rack removes a large heat source from the IT chassis and, as NVIDIA notes, frees space for compute and improves cooling. In the Mt. Diablo spec the sidecar itself is fully air-cooled, which keeps the water loop away from the high-voltage power electronics.

The coupling also creates failure modes that cross the boundary. A coolant pump or CDU failure at 1 MW leaves very little thermal mass in the loop: the time to throttle or trip is measured in seconds, so the power system must be able to reduce load on a cooling alarm rather than simply keep delivering. Likewise a power-bus event that drops the pumps will cascade into a thermal event. Design reviews should treat the pump power supply as critical load on the same DC bus, with its own protection selectivity.

Grid Interconnect, Timelines and Honest Uncertainties

The 800 VDC story does not stop at the building wall. A 100 MW AI campus is a transmission-class customer, and the SST or perimeter rectifier is the interface to the utility. Four considerations dominate.

First, voltage class. The 13.8 kV figure NVIDIA cites is a typical distribution-level voltage in the US; sites at 33 or 34.5 kV need a converter rated for the higher input, which is why the SolarEdge and Infineon concept spans 13.8 to 34.5 kV. Second, reliability: a single large perimeter converter concentrates risk, so designs use many parallel modules with fault isolation. Third, power quality and grid codes: converters must meet harmonic, flicker and ride-through requirements. Fourth, black-start and islanding: if the campus is paired with on-site generation, the DC bus makes it easier to combine fuel cells, solar and batteries (all native DC sources) without intermediate AC conversion, a point that connects to the behind-the-meter strategies in our power supply analysis.

For the industrial side of the story, where physical AI and factory twins will themselves become heavy data center customers, see the post on industrial world models and physical AI for factory autonomy.

Timeline: what is known and what is not

May 2025: NVIDIA publishes the 800 VDC architecture blog and Google announces its plus/minus 400 VDC and 1 MW rack direction.
November 2025: SolarEdge and Infineon announce an SST development program (still in development at announcement, no commercial date).
October 2026: OCP Mt. Diablo disaggregated power rack specification v1.0.0 final; Infineon and Eaton announce SiC collaboration for an MVSST 2.0 platform.
2027: NVIDIA states full-scale 800 VDC data center production should coincide with Kyber rack-scale systems.

What remains unverified or genuinely uncertain: whether SST efficiency at real part-load will beat a transformer plus rectifier line-up; which voltage configuration, 800 V two-wire or plus/minus 400 V, becomes the volume standard; the pace of code and inspector acceptance; the supply chain for 2.3 to 3.3 kV SiC modules; and whether utilities will tolerate large synchronous AI loads. The headline claims of 5% efficiency, 70% maintenance savings and 30% TCO come from the architecture’s sponsor and are, at best, estimates until multi-year operating data exists.

Trade-offs, Gotchas, and What Goes Wrong

Single-point-of-failure concentration. Centralising conversion removes thousands of small power supplies and replaces them with a few large modules. Per-unit reliability can be higher, but a failure now takes down more load. Mitigation is N+1 or N+2 modular redundancy with hot-swap, and sectionalised DC buses with selective protection, which is more complicated to coordinate than AC.

Protection coordination at microsecond timescales. In an AC system, upstream breakers are time-graded to trip after downstream ones. When a faulted branch must clear in microseconds, an SSCB downstream and a fuse upstream can be selective only if their let-through energies are characterised together. A bad coordination study yields a nuisance trip that kills a whole row rather than one rack.

Capacitive inrush and precharge. Connecting a rack with large input capacitance to a live 800 V bus draws a very large inrush unless there is controlled precharge. Hot-swap of racks and power shelves requires precharge circuits and sequenced contactors, and a failed precharge resistor is a common field failure in high-voltage DC systems.

Stray and ground-fault currents. Mixed AC and DC grounding can create corrosion currents and nuisance detection trips. The ground fault monitoring scheme must be designed as a system, including the IT equipment, not bolted on afterwards.

Workforce and tooling. Technicians trained on 480 VAC lockout/tagout need new procedures, meters rated for 800 VDC and DC-rated arc-flash PPE. A DC bus with large capacitors stays lethal after isolation unless discharge is verified.

Lock-in and standards risk. If the market splits between 800 V two-wire and plus/minus 400 V, connectors, busbars and converters could be stranded. The close electrical relationship of the two (the Mt. Diablo spec itself includes an 800 V differential option) lowers that risk, but buyers should ask vendors which configuration their equipment supports and whether field upgrade is possible.

Retrofits. Brownfield AC halls cannot cheaply convert. The efficiency case is strongest for greenfield sites designed around 100 kW to 1 MW racks. A hybrid with Mt. Diablo-style sidecars is the realistic bridge for existing halls.

Practical Recommendations

If you are planning AI capacity for 2027 and beyond, treat the voltage decision as a design-time choice, because it is expensive to change after the building is poured. For racks below roughly 100 kW per rack, conventional AC with 54 V shelves remains sound, and nothing here argues for ripping it out. For racks above 200 kW, where NVIDIA itself says the 54 V design hits limits, evaluate a sidecar or 800 V DC distribution seriously, and make the evaluation numerical rather than rhetorical.

A short checklist:

Build your own chain-efficiency model with vendor-supplied part-load curves, not nameplate figures, and include fan and cooling overhead for each stage.
Ask SST vendors for measured efficiency from 10% to 100% load, auxiliary power, fault-current limiting behaviour and mean time between failures of the series cells.
Specify the protection scheme and coordination study up front, including arc-flash incident energy at each boundary.
Decide the grounding scheme (solid or high-resistance midpoint) against your availability target and write the first-fault procedure.
Size storage for two time scales: capacitors for load smoothing, batteries for ride-through, and check compliance with UL 9540/9540A and NFPA 855.
Put pump and CDU power on the same selective-protection design as the compute.
Insist on a path from 400 V to 800 V differential operation, and on connector interoperability, to limit stranded-asset risk.
Plan for training and procedures before energisation, not after.

Frequently Asked Questions

What is an 800V DC data center?

It is a facility that converts medium-voltage grid power (for example 13.8 kV AC) to about 800 volts direct current once, near the building edge, and distributes that DC to racks. Inside the rack an isolated DC-DC converter steps it down to 54 V or 12 V. NVIDIA proposes it for racks of 1 MW and beyond, with full-scale production tied to Kyber systems in 2027.

Why not just use higher AC voltage instead of DC?

AC can go higher, but it carries reactive power, skin-effect losses and requires a rectifier in every rack. NVIDIA reports 800 V DC busways carry 85% more power than 415 VAC through the same conductor size and use 45% less copper. DC also simplifies integration of batteries and other DC sources. The trade-off is harder protection and less mature codes.

What is a solid-state transformer and why does it matter?

An SST uses SiC power electronics, a high-frequency isolation transformer and a controller to convert MV AC directly to DC, replacing a heavy line-frequency transformer plus rectifier. It is smaller, controllable and can limit faults quickly. Announced designs target 13.8 to 34.5 kV input and 800 to 1500 V output, but efficiency claims above 99% are still development targets.

Is 800 VDC the same as the OCP Mt. Diablo plus/minus 400 VDC standard?

Not identical, but closely related. Mt. Diablo, authored by Microsoft, Meta and Google, outputs plus/minus 400 VDC with a common return, and offers an 800 VDC differential option. It is a sidecar rack that still rectifies AC. NVIDIA’s end state rectifies at the perimeter. Both aim at 1 MW class racks.

How much more efficient is 800 VDC?

NVIDIA claims up to 5% better end-to-end efficiency than 54 V systems. Google cites about 3% for its AC-to-DC sidecar approach. Our illustrative chain model above shows about 5 points from removing stages, but real results depend on part-load behaviour and cooling overhead, and no multi-year field data is public yet.

When will 800 VDC be deployed at scale?

NVIDIA says full-scale production should coincide with Kyber rack-scale systems in 2027. The OCP Mt. Diablo specification was finalised in October 2026, and SST platforms from vendors such as Eaton, SolarEdge and Infineon are in development. Expect early pilots and sidecar-based hybrids first, with perimeter DC conversion following as protection and codes mature.

800V DC Power for AI Data Centers: Solid-State Transformers, Rack Architecture and Efficiency Math (2026)